The present invention relates to a data multiplexing device for multiplexing pattern data or similar data.
A data multiplexing device is usually employed for generating pattern data at a rate as high as 3 giga bits, for instance. FIG. 1 shows an example of a conventional data multiplexing device, which includes two front-stage data multiplexing circuits 10 and 20 and one back-stage data multiplexing circuit 30.
The data multiplexing circuits 10, 20 and 30 are multiplexers for multiplexing input 2-channel input data on a time-shared basis and they have frequency dividers 11, 21 and 31, respectively. The frequency dividers 11, 21 and 31 are 1/2 frequency dividers, each formed by a T flip-flop, for example. The frequency divider 31 frequency divides a clock CL available at a terminal 40, and the frequency dividers 11 and 21 both frequency divide an output D5 of the frequency divider 31.
In the data multiplexing circuit 10 input pattern data I1 and an output D1 of the frequency divider 11 are supplied to an AND gate 12, input pattern data I3 and the other output D3 of the frequency divider 11 are supplied to an AND gate 13, and the outputs of the AND gates 12 and 13 are provided to an OR gate 14. In the data multiplexing circuit 20 input pattern data I2 and an output D2 of the frequency divider 21 are applied to an AND gate 22, input pattern data I4 and the other output D4 of the frequency divider 21 are applied to an AND gate 23, and the outputs of the AND gates 22 and 23 are provided to an OR gate 24. In the data multiplexing circuit 30 output pattern data O1 of the data multiplexing circuit 10 and the output D5 of the frequency divider 31 are applied to an AND gate 32, output pattern data O2 of the data multiplexing circuit 20 and the other output D6 of the frequency divider 31 are applied to an AND gate 33, and the outputs of the AND gates 32 and 33 are provided to an OR gate 34.
The input pattern data I1, I2, I3 and I4 each have a NRZ waveform of a rate 1/4 of the clock CL (i.e. a period four times that of the clock CL). At the start of the system an initial reset signal IN is applied from a terminal 50 to the frequency dividers 11, 21 and 31 to rest them.
Consequently, the clock CL, the outputs D5 and D6 of the frequency divider 31, the outputs D1 and D3 of the frequency divider 11, the outputs D2 and D4 of the frequency divider 21, the input pattern data I1, I3, I2 and I4, the output pattern data O1 and O2 of the data multiplexing circuits 10 and 20, final output pattern data O3 available from the data multiplexing circuit 30 and the initial reset signal IN bear such relations as shown in FIG. 2. The input pattern data I1 through I4 are time division multiplexed in the order I1-I2-I3-I4-I1-I2- . . . , providing the output pattern data O3.
In the conventional data multiplexing device in which the frequency dividers 11 and 21 operate concurrently, it is necessary, for varying the frequency of the clock CL over a wide band, to switch the frequency range of the clock CL or switch an output amplifier in accordance with the frequency range. This may sometimes produce in the clock CL pulses P1 and P2 of widths smaller than a predetermined value, resulting in the production of a narrow pulse P3 in the output D5 of the frequency divider 31 as exemplified in FIG. 3. Alternatively, clock pulse or pulses may drop out. In the case where the source of the clock CL is an external unit which is connected to the data multiplexer, a similar unwanted phenomenon occurs when the connection is unstable.
In such a conventional data multiplexing device designed so that the frequency dividers 11 and 21 operate concurrently, if the frequency dividers 11 and 21 differ in response speed, for example, fi the frequency divider 21 is slower in response than the frequency divider 21, when the narrow pulse P3 occurs in the output D5 of the frequency divider 31 which serves as a clock for the frequency dividers 11 and 21 as mentioned above, the frequency divider 11 will respond to the narrow pulse P3 but the frequency divider 21 will not respond. In such an instance, the outputs D1 and D2 of the frequency dividers 11 and 21 and the outputs D3 and D4 of the frequency dividers 11 and 21 will differ from each other as depicted in FIG. 3. This state lasts even after the clock CL becomes normal again and consequently the output D5 of the frequency divider 31 returns to its normal state. Hence, the order of multiplexing of the input pattern data I1 through I4 in the final output pattern data O3 available from the data multiplexing circuit 30 becomes different from the predetermined order after the occurrence of an abnormality in the clock CL.
In the prior art, when such abnormalities as mentioned above occur in the clock CL and in the outputs D5 and D6 of the frequency divider 31 and the order of multiplexing of the input pattern data I1 to I4 in the output pattern data O3 become different from the predetermined order due to the difference in response between the frequency dividers 11 and 21, a reset signal is supplied, by an artificial operation, from the terminal 50 to the frequency dividers 11, 21 and 31 to reset them, thus correcting the order of multiplexing of the input pattern data I1 through I4 to the predetermined order.
However, the restoration of normal operation by such an artificial operation is troublesome. Besides, according to the cause of the abnormality in the clock CL, there is a case where it cannot be recognized that the order of multiplexing of the input pattern data has become different from the predetermined order, and in such a case, the order of multiplexing cannot be corrected.